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a u s t ri a m i c r o s y s t e m s
AS1530, AS1531
1 2 - B i t , S i n g l e - S u p p l y, L o w - P o w e r, 4 0 0 / 3 0 0 k s ps A/ D Conv e rters
D a ta S he e t
1 General Description
The AS1530/AS1531 are low-power, 4/8-channel, 400/ 300ksps, 12-bit analog-to-digital (A/D) converters specifically designed to operate with single-supply devices. Superior AC characteristics, very low power consumption, and highly-reliable packaging make these ultrasmall devices perfect for battery-powered remote-sensor and data-acquisition devices. The successive-approximation register (SAR), highspeed sampling, high-bandwidth track/hold circuitry, and multi-mode operation combine to make these devices highly-flexible and configurable. Both devices require low supply current (2.8mA @ 400ksps, AS1530; 2.2mA @ 300ksps, AS1531) and feature a reduced-power mode and a power-down mode to lower power consumption at slower throughput rates. The devices operate from a single supply (+4.5 to +5.5V, AS1530; +2.7 to +3.6V, AS1531). Both devices contain an internal 2.5V reference, an integrated reference buffer, and feature support for an external reference (1V to VDD). Data accesses are made via the high-speed, 4-wire, SPI, QSPI-, and Microwire-compatible serial interface. The devices are available in a 20-pin TSSOP package. For lower-speed versions of these devices, contact austriamicrosystems, AG regarding the AS1526/AS1527 A/D converters. Figure 1. Block Diagram and Pin Assignments
17 CSN 18 SCLK 16 DIN Input Shift Register Output Shift Register
2 Key Features
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Single-Supply Operation: - +4.5 to +5.5V (AS1530) - +2.7 to +3.6V (AS1531) Sampling Rate: - 400ksps (AS1530) - 300ksps (AS1531) Software-Configurable Analog Input Types: - 8-Channel Single-Ended - 8-Channel Pseudo Differential Referenced to COM - 4-Channel Pseudo Differential - 4-Channel Fully Differential Software-Configurable Input Range Internal +2.5V Reference Low-Current Operation: - 2.8mA @ 400ksps (AS1530) - 2.2mA @ 300ksps (AS1531) - 0.4mA in Reduced-Power Mode - 0.5A in Full Power-Down Mode SPI/QSPI/Microwire/TMS320-Compatible 20-pin TSSOP Package
!
!
! ! !
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3 Applications
The devices are ideal for remote sensors, data-acquisition and data-logging devices, pen-digitizers, process control, or any other space-limited A/D application with low power-consumption requirements.
14 DOUT 15 SSTRB
CH0 1 CH1 2
20 VDD1 19 VDD2 18 SCLK 17 CSN
AS1530/ AS1531
12-Bit SAR
10 VDD3 19 VDD2
CH2 3 CH3 4 CH4 5 CH5 6 CH6 7
Control Logic 1:8 CH0:CH7 9 COM 12 REFADJ 11 REF +1.2V REF Analog Input Track/ Hold 17k Av 2.05 +2.50V IN
AS1530/ AS1531
16 DIN 15 SSTRB 14 DOUT 13 GND 12 REFADJ 11 REF
OUT REF 20 VDD1
CH7 8 COM 9 VDD3 10
13 GND
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Contents
1 General Description ................................................................................................................................ 1 2 Key Features .......................................................................................................................................... 1 3 Applications ............................................................................................................................................ 1 4 Absolute Maximum Ratings .................................................................................................................... 3 5 Electrical Characteristics ........................................................................................................................ 4
AS1530 Electrical Characteristics .......................................................................................................................... 4 AS1531 Electrical Characteristics .......................................................................................................................... 6 Timing Characteristics ............................................................................................................................................ 8
6 Typical Operating Characteristics ......................................................................................................... 10 7 Pinout ................................................................................................................................................... 13
Pin Assignments ................................................................................................................................................... 13 Pin Descriptions ................................................................................................................................................... 13
8 Detailed Description ............................................................................................................................. 14
Analog Input ......................................................................................................................................................... 14 Input Protection ............................................................................................................................................. 14 Track/Hold ............................................................................................................................................................ 14 Control Register ................................................................................................................................................... 15 Analog Input Configuration ................................................................................................................................... 15 Channel Selection ................................................................................................................................................ 16 Single-Ended Input ........................................................................................................................................ 16 Differential Input ............................................................................................................................................ 16 Starting a Conversion ........................................................................................................................................... 17 Transfer Functions ................................................................................................................................................ 18 Power Modes ....................................................................................................................................................... 19 Reduced Power Mode ................................................................................................................................... 20 Full Power-Down Mode ................................................................................................................................. 20 Reference ............................................................................................................................................................. 21 Internal Reference ......................................................................................................................................... 21 External Reference ....................................................................................................................................... 22
9 Application Information ......................................................................................................................... 23
Initialization ........................................................................................................................................................... 23 Serial Interface ..................................................................................................................................................... 23 Serial Interface Configuration ........................................................................................................................ 23 QSPI Interface ............................................................................................................................................... 24 Quick Evaluation Circuit ....................................................................................................................................... 25 Layout Considerations .......................................................................................................................................... 26
10 Package Drawings and Markings ....................................................................................................... 27 11 Ordering Information ........................................................................................................................... 28
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4 Absolute Maximum Ratings
Stresses beyond those listed in Table 1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 1. Absolute Maximum Ratings Parameter VDD1, VDD2, VDD3 to GND VDD1 to VDD2 to VDD3 CH0:CH7, COM to GND REF, REFADJ to GND DIN, SCLK, CSN, to GND DOUT, SSTRB to GND DOUT, SSTRB Sink Current Continuous Power Dissipation (TAMB = +70C) Operating Temperature Range Storage Temperature Range -40 -60 Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max +7 +0.3 VDD1 + +0.3 VDD1 + +0.3 VDD2 + +0.3 VDD2 + +0.3 25 559 +85 +150 Units V V V V V V mA mW C C The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C "Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". The lead finish for Pb-free leaded packages is matte tin (100% Sn). Derate 7.0mW/C above +70C Comments
Package Body Temperature
+260
C
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5 Electrical Characteristics
AS1530 Electrical Characteristics
VDD1 = VDD2 = VDD3 = +4.5 to +5.5V, COM = GND, fSCLK= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5V at REF, REFADJ = VDD1, TAMB = TMIN to TMAX (unless otherwise specified). Typ values at TAMB = +25C. Table 2. AS1530 Electrical Characteristics Symbol DC Accuracy INL DNL
1
Parameter Resolution Relative Accuracy Differential Nonlinearity Offset Error
2
Conditions
Min 12 -1
Typ
Max
Units Bits
+1 +1 +6
LSB LSB LSB
No missing codes over temperature
-1 -6
3 -6 +6 LSB Gain Error Gain-Error Temperature ppm/ 1.6 Coefficient C Channel-to-Channel 0.2 LSB Offset Error Matching Dynamic Specifications: 100kHz sinewave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bit RANGE (page 15) = 0, pseudo-differential input mode Signal-to-Noise plus SINAD 70 dB Distortion Ratio THD Total Harmonic Distortion Up to the 5th harmonic -82 dB Spurious-Free SFDR 83 dB Dynamic Range IMD Intermodulation Distortion fIN1 = 99kHz, fIN2 = 102kHz 76 dB Channel-to-Channel fIN = 200kHz, VIN = 2.5Vp-p -85 dB 4 Crosstalk Full-Power Bandwidth -3dB point 6 MHz Full-Linear Bandwidth SINAD > 68dB 450 kHz Conversion Rate
Conversion Time tACQ Track/Hold Acquisition Time tAD Aperture Delay tAJ Aperture Jitter fSCLK Serial Clock Frequency Duty Cycle Analog Inputs: CH0:CH7, COM VCHx - Input Voltage Range: SingleEnded, Pseudo-Differential, VCHy 6 (COM) and Differential Multiplexer Leakage Current Input Capacitance Internal Reference VREF REF Output Voltage REF Short-Circuit Current REF Output Temperature TCVREF Coefficient Load Regulation CBYPREF
7
tCONV
5
2.5 390 7 <50 0.5 40 Bit RANGE (page 15) = 1 Bit RANGE (page 15) = 0 On/off leakage current, VCHx = 0 or VDD1 6.4 60
s ns ns ps MHz %
0 VREF -VREF +VREF /2 /2 -1 0.001 +1 18 2.48 2.50 30 25 2.52
V A pF V mA ppm/ C mV/ mA F
TAMB = +25C
0 to 1mA output load 4.7
1.2
4.0 10
Capacitive Bypass at REF
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Table 2. AS1530 Electrical Characteristics (Continued) Parameter Conditions Capacitive Bypass at CBYPREF ADJ REFADJ REFADJ Output Voltage REFADJ Input Range For small adjustments, from 1.22V REFADJ Buffer Disable To power down the internal reference Threshold Buffer Voltage Gain External Reference: Reference buffer disabled, reference applied to pin REF REF Input Voltage Range
8
Symbol
Min 0.01
Typ
Max 10
Units F V mV
1.22 100 1.4 2.045 VDD1 + 50mV 200 350 320 5 0.7 x VDD 0.3 x VDD 0.2 VDD1 1
V V/V
1.0 VREF = 2.50V, fSCLK = 6.4MHz VREF = 2.50V, fSCLK = 0 Power-Down, fSCLK = 0
V
REF Input Current Digital Inputs: DIN, SCLK, CSN VINH VINL Input High Voltage Input Low Voltage
A
V V V A pF V V A pF
VHYST Input Hysteresis IIN Input Leakage CIN Input Capacitance Digital Outputs: DOUT, SSTRB VOL Output Voltage Low VOH Output Voltage High IL Tri-State Leakage Current COUT Tri-State Output Capacitance Power Supply VDD1, 9 VDD2, Positive Supply Voltage VDD3
VIN = 0 or VDD2
-1 5
+1
ISINK = 5mA ISOURCE = 1mA CSN = VDD2 CSN = VDD2
0.4 4 -10 5 +10
4.5 Normal Operation with 10 External Reference Normal Operation with 10 Internal Reference Reduced-Power Mode Full Power-Down Mode
11
5.5 2.8 3.3 0.4 0.5 3.3 3.8 0.8 2 +2
V
IVDD1, IVDD2, IVDD3
Supply Current
VDD1 = VDD2 = VDD3 = 5.5V
mA
A mV
PSR
Power-Supply Rejection
VDD1 = VDD2 = VDD3 = 5V 10%
-2
0.1
1. Tested at VDD1 = VDD2 = VDD3 = +5V, COM = GND, bit RANGE (page 15) = 1, single-ended input mode. 2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nulled. 3. Offset nulled. 4. Ground on channel; sinewave applied to all off channels. 5. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. 6. The absolute voltage range for the analog inputs (CH0:CH7, and COM) is from GND to VDD1. 7. External load should not change during conversion for specified accuracy. Guaranteed specification of 4mV/mA is a result of production test limitations. 8. AS1530/AS1531 performance is limited by the device noise floor, typically 300Vp-p.
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9. Electrical characteristics are guaranteed from VDD1(MIN) = VDD2(MIN) = VDD3(MIN) to VDD1(MAX) = VDD2(MAX) = VDD3(MAX). For operations beyond this range, see Typical Operating Characteristics on page 10. For guaranteed specifications beyond the limits, contact austriamicrosystems, AG. 10. AIN = mid-scale; bit RANGE (page 15) = 1; tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 6.4MHz @ GND to VDD2. 11. SCLK = DIN = GND, CSN = VDD2.
AS1531 Electrical Characteristics
VDD1 = VDD2 = VDD3 = +2.7 to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5V at REF, REFADJ = VDD1, TAMB = TMIN to TMAX (unless otherwise specified). Typ values at TAMB = +25C. Table 3. AS1531 Electrical Characteristics Symbol DC Accuracy INL DNL
1
Parameter Resolution Relative Accuracy Differential Nonlinearity Offset Error
2
Conditions
Min 12 -1
Typ
Max
Units Bits
+1 +1 +6
LSB LSB LSB LSB ppm/ C LSB
No missing codes over temperature
-1 -6
3 -6 +6 Gain Error Gain-Error Temperature 1.6 Coefficient Channel-to-Channel Offset 0.2 Error Matching Dynamic Specifications: 75kHz sinewave input, 2.5Vp-p, 300ksps, 4.8MHz clock, bit RANGE (page 15) = 0, pseudo-differential input mode Signal-to-Noise plus SINAD 70 Distortion Ratio THD Total Harmonic Distortion Up to the 5th harmonic -81 Spurious-Free Dynamic SFDR 84 Range 76 IMD Intermodulation Distortion fIN1 = 73kHz, fIN2 = 77kHz Channel-to-Channel fIN = 150kHz, VIN = 2.5Vp-p -80 4 Crosstalk Full-Power Bandwidth -3dB point 6 Full-Linear Bandwidth SINAD > 68dB 350 Conversion Rate
dB dB dB dB dB MHz kHz s
Conversion Time tACQ Track/Hold Acquisition Time tAD Aperture Delay tAJ Aperture Jitter Serial Clock Frequency fSCLK Duty Cycle Analog Inputs: CH0:CH7, COM VCHx - Input Voltage Range: SingleEnded, Pseudo-Differential, VCHy 6 (COM) and Differential Multiplexer Leakage Current Input Capacitance Internal Reference REF Output Voltage VREF REF Short-Circuit Current
tCONV
5
Normal operation Normal operation
3.3 520 7 <50
Normal operation
0.5 40
4.8 60
ns ns ps MHz %
Bit RANGE (page 15) = 1 Bit RANGE (page 15) = 0 On/off leakage current, VCHx = 0 or AVDD
0 VREF +VREF -VREF /2 /2 -1 0.001 +1 18 2.48 2.50 30 2.52
V A pF V mA
TAMB = +25C
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Table 3. AS1531 Electrical Characteristics (Continued) Symbol TCVREF Parameter REF Output Temperature Coefficient Load Regulation CBYPREF CBYPREF
7
Conditions
Min
Typ 25
Max
0 to 0.75mA output load 4.7 0.01
0.6
2.0 10 10
Capacitive Bypass at REF Capacitive Bypass ADJ at REFADJ REFADJ Output Voltage REFADJ Input Range For small adjustments, from 1.22V REFADJ Buffer To power down the internal reference Disable Threshold Buffer Voltage Gain External Reference: Reference buffer disabled, reference applied to REF REF Input Voltage Range REF Input Current Digital Inputs: DIN, SCLK, CSN VINH VINL Input High Voltage Input Low Voltage
8
Units ppm/ C mV/ mA F F V mV
1.22 100 1.4 2.045 1.0 VDD1 + 50mV 350 320 5 VDD1 -1
V V/V V A
VREF = 2.50V, fSCLK= 4.8MHz VREF = 2.50V, fSCLK = 0 In power-down, fSCLK = 0 0.7 x VDD
200
V 0.3 x VDD 0.8 V V A pF V V +10 5 A pF
VHYST Input Hysteresis Input Leakage IIN Input Capacitance CIN Digital Outputs: DOUT, SSTRB Output Voltage Low VOL VOH IL Output Voltage High
VIN = 0 or VDD2
-1 5
+1
ISINK = 5mA ISOURCE = 0.5mA CSN = VDD2 CSN = VDD2 VDD2 0.5V -10
0.4
Tri-State Leakage Current Tri-State Output COUT Capacitance Power Supply VDD1, 9 VDD2, Positive Supply Voltage VDD3
2.7 Normal Operation with External 10 Reference Normal Operation with Internal 10 Reference Reduced-Power 11 Mode Full Power-Down 11 Mode VDD1 = VDD2 = VDD3 = 2.7 to 3.6V, Mid-Scale Input
3.6
V
2.2
2.7
IVDD1, IVDD2, IVDD3
Supply Current
VDD1 = VDD2 = VDD3 = 5.5V
2.7 0.4 0.5 -2 0.1
3.2 mA 0.8 2 +2 A mV
PSR
Power-Supply Rejection
1. Tested at VDD1 = VDD2 = VDD3 = +3V; COM = GND; bit RANGE (page 15) = 1, single-ended input mode.
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2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nulled. 3. Offset nulled. 4. Ground on channel; sinewave applied to all off channels. 5. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. 6. The absolute voltage range for the analog inputs (CH0:CH7, and COM) is from GND to VDD1. 7. External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA is a result of production test limitations. 8. AS1530/AS1531 performance is limited by the device noise floor, typically 300Vp-p. 9. Electrical characteristics are guaranteed from VDD1(MIN) = VDD2(MIN) = VDD3(MIN) to VDD1(MAX) = VDD2(MAX) = VDD3(MAX). For operations beyond this range, see Typical Operating Characteristics on page 10. For guaranteed specifications beyond the limits, contact austriamicrosystems, AG. 10. AIN = mid-scale; bit RANGE (page 15) = 1; tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 4.8MHz @ GND to VDD2. 11. SCLK = DIN = GND, CSN = VDD2.
Timing Characteristics
Table 4. AS1530 Timing Characteristics - (Figures 2, 3, 21, 23; VDD1 = VDD2 = VDD3 = +4.5 to +5.5V; TAMB = TMIN to TMAX (unless otherwise specified). Symbol tCP tCH tCL tDS tDH tCSS tCS0 tDOH tSTH tSTV tDOV tDOD tSTD tDOE tSTE tCSW Parameter SCLK Period SCLK Pulse Width High SCLK Pulse Width Low DIN to SCLK Setup DIN to SCLK Hold CSN Fall to SCLK Rise Setup SCLK Rise to CSN Fall Ignore SCLK Rise to DOUT Hold SCLK Rise to SSTRB Hold SCLK Rise to DOUT Valid SCLK Rise to SSTRB Valid CSN Rise to DOUT Disable CSN Rise to SSTRB Disable CSN Fall to DOUT Enable CSN Fall to SSTRB Enable CSN Pulse Width High CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF 100 10 10 Conditions Min 156 62 62 35 0 35 35 10 10 20 20 80 80 65 65 65 65 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 5. AS1531 Timing Characteristics - (Figures 2, 3, 21, 23; VDD1 = VDD2 = VDD3 = +2.7 to +3.6V; TAMB = TMIN to TMAX (unless otherwise specified). Symbol tCP tCH tCL tDS tDH tCSS tCS0 tDOH tSTH Parameter SCLK Period SCLK Pulse Width High SCLK Pulse Width Low DIN to SCLK Setup DIN to SCLK Hold CSN Fall to SCLK Rise Setup SCLK Rise to CSN Fall ignore SCLK Rise to DOUT Hold SCLK Rise to SSTRB Hold CLOAD = 20pF CLOAD = 20pF Conditions Min 208 83 83 45 0 45 45 13 13 20 20 Typ Max Units ns ns ns ns ns ns ns ns ns
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Table 5. AS1531 Timing Characteristics - (Figures 2, 3, 21, 23; VDD1 = VDD2 = VDD3 = +2.7 to +3.6V; TAMB = TMIN to TMAX (unless otherwise specified). (Continued) Symbol tDOV tSTV tDOD tSTD tDOE tSTE tCSW Parameter SCLK Rise to DOUT Valid SCLK Rise to SSTRB Valid CSN Rise to DOUT Disable CSN Rise to SSTRB Disable CSN Fall to DOUT Enable CSN Fall to SSTRB Enable CSN Pulse Width High Conditions CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF 100 13 13 Min Typ Max 100 100 85 85 85 85 Units ns ns ns ns ns ns ns
Figure 2. DOUT Enable-Time Load Circuits
VDD2 DOUT 6k CLOAD 20pF
6k DOUT CLOAD 20pF
DGND
GND
High-impedance to VOH and VOL to VOH
DGND High-impedance to VOL and VOH to VOL
Figure 3. DOUT Disable-Time Load Circuits
VDD2 DOUT 6k CLOAD 20pF
6k DOUT CLOAD 20pF
DGND VOH to high-impedance
GND
DGND VOL to high-impedance
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6 Typical Operating Characteristics
Figure 4. INL vs. Digital Output Code
0.6 0.4
Figure 5. DNL vs. Digital Output Code
0.6 0.4
INL (LSB) e
0.2 0 -0.2 -0.4 -0.6 0 500 1 000 1 500 2000 2500 3000 3500 4000 4500
DNL (LSB) e
0.2 0 -0.2 -0.4 -0.6 0 500 1 000 1 500 2000 2500 3000 3500 4000 4500
Digital Output Code
Figure 6. FFT @ 10kHz; RANGE = 1, MODE = 1
20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 0 20 40 60 80 100 120 140 160
Digital Output Code
Figure 7. FFT @ 75kHz; RANGE = 0, MODE = 1
20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 0 20 40 60 80 100 120 140 160
FFT (dBC) e
Input Signal Frequency (kHz)
Figure 8. ENOB vs. VREF; 1st Order 300kHz Low Pass Filter
11.6 11.5 11.4
FFT (dBC) e
Input Signal Frequency (kHz)
Figure 9. ENOB vs. Input Signal Frequency; 1st Order 300kHz Low Pass Filter
11.45 11.4 11.35
ENOB (Bit) e
ENOB (Bit)
11.3 11.2 11.1 11 10.9 10.8 10.7 1 1.4 1.8 2.2 2.6 3
11.3 11.25 11.2 11.15 11.1 11.05 0 50 100 150 200 250 300 350
Voltage (V)
Frequency (kHz)
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Data Sheet
Figure 10. IVDD vs. VDD (Static)
4 3.5
Figure 11. IVDD vs. Temperature; Internal Reference
4
Supply Current (mA) e
3 2.5 2 1.5 1 0.5 0
Supply Current (mA) e
Internal Reference
3.75 3.5 3.25 3 2.75 2.5 -40 -15 10 35 60 85
AS1530
External Reference
AS1531
2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
Supply Voltage (V)
Figure 12. IVDD vs. VDD (Converting)
3 2.5 2 1.5 1 0.5 0 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
Reduced Power Mode; Internal Reference Reduced Power Mode; External Reference Normal Operation; Internal Reference
Temperature (C)
Figure 13. IVDD vs. Temperature (Static)
2
Supply Current (mA) e
Supply Current (mA)
1.5
1
AS1530, Reduced Power Mode, Internal Ref. AS1531, Reduced Power Mode, Internal Ref.
0.5
AS1530, Reduced Power Mode, External Ref. AS1531, Reduced Power Mode, External Ref.
0 -40 -15 10 35 60 85
Supply Voltage (V)
Figure 14. VREF vs. Temperature
2.51
Temperature (C)
Figure 15. Offset Error vs. VDD
-1
Reference Voltage (V) .
2.5
Offset Error (LSB) .
2.505
-1.2
-1.4
2.495
-1.6
2.49 -40 -15 10 35 60 85
-1.8 2.7 3.4 4.1 4.8 5.5
Temperature (C)
Supply Voltage (V)
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Data Sheet
Figure 16. Offset Error vs. Temperature
-1
Figure 17. Gain Error vs. VDD
3 2
Offset Error (LSB) .
Gain Error (LSB) e
-1.2
1 0 -1 -2
-1.4
-1.6
-1.8 -40 -15 10 35 60 85
-3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
Temperature (C)
Figure 18. Gain Error vs. Temperature
5 4 3 2 1 0 -40 -15 10 35 60 85
VDD (V)
Gain Error (LSB) e
Temperature (C)
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Data Sheet
7 Pinout
Pin Assignments
Figure 19. Pin Assignments (Top View)
CH0 1 CH1 2 CH2 3 CH3 4 CH4 5 CH5 6 CH6 7 CH7 8 COM 9 VDD3 10 20 VDD1 19 VDD2 18 SCLK 17 CSN
AS1530/ AS1531
16 DIN 15 SSTRB 14 DOUT 13 GND 12 REFADJ 11 REF
Pin Descriptions
Table 6. Pin Descriptions Pin Number Pin Name Description Analog Sampling Inputs. These eight pins serve as analog sampling inputs. Common Analog Inputs. Tie this pin to ground in single-ended mode. Positive Supply Voltage Reference-Buffer Output/A/DC Reference Input. This pin serves as the reference voltage for analog-to-digital conversions. In internal reference mode, the reference buffer provides a +2.50V nominal output, externally adjustable at pin REFADJ. In external reference mode, disable the internal buffer by pulling pin REFADJ to VDD1. Reference-Buffer Amplifier Input. To disable the reference-buffer amplifier, tie this pin to VDD1. Analog and Digital Ground Serial Data Output. Data is clocked out at the rising edge of pin SCLK. DOUT is high impedance when CSN is high. Serial Strobe Output. SSTRB pulses high for one clock period before the MSB is clocked out. SSTRB is high impedance when CSN is high. Serial Data Input. Data is clocked in at the rising edge of SCLK. Active-Low Chip Select. Data will not be clocked into pin DIN unless CSN is low. When CSN is high, pins DOUT and SSTRB are high impedance. Serial Clock Input. This pin clocks data into and out of the serial interface, and is used to set the conversion speed. Note: The duty cycle must be between 40 and 60%. Positive Supply Voltage Positive Supply Voltage
1:8 9 10 11
CH0:CH7 COM VDD3 REF
12 13 14 15 16 17 18 19 20
REFADJ GND DOUT SSTRB DIN CSN SCLK VDD2 VDD1
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Analog Input
Data Sheet
8 Detailed Description
Analog Input
The equivalent input circuit (Figure 20) shows the input architecture: track/hold circuitry, input multiplexer, input comparator, switched-capacitor DAC, and internal reference. A flexible serial interface provides easy connections to various microprocessors.
Figure 20. Equivalent Input Circuit
REF CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM Analog Input Multiplexer
CHOLD 13F AIN+ CSWITCH 11F -+ Sample Switch CHOLD 13F AINCSWITCH 11F -+ RIN
+ - Comparator
CSWITCH includes all parasitics
The input tracking circuitry has a 6MHz small-signal bandwidth, thus it is possible to under-sample (digitize high-speed transient events) and measure periodic signals modulated at frequencies exceeding the AS1530/AS1531 sampling rate.
Note: To avoid high-frequency signals being aliased into the frequency band of interest, antialias filtering is recommended
Input Protection
Internal protection diodes (which clamp the analog input to VDD1 and GND) allow the channel inputs to swing from (GND to 0.3V) to (VDD1 + 0.3V) without damaging the devices. However, for accurate conversions near full scale, the inputs must not exceed VDD1 by more than 50mV or be lower than GND by 50mV.
Note: If the analog input exceeds 50mV beyond the supply voltage, do not allow the input current to exceed 2mA.
Track/Hold
The track/hold stage enters tracking mode on the rising edge of SCLK which clocks in bit MODE of the 8-bit control byte (see Figure 21 on page 17). The track/hold stage enters hold mode on the falling clock edge after bit PD0 of the 8bit control byte has been shifted in. The time required for the track/hold circuit to acquire an input signal is a function of how quickly the input capacitance is charged. If the input signal source impedance is high, the acquisition time lengthens. The acquisition time (tACQ) is the maximum time the device takes to acquire the signal and is also the minimum time needed for the signal to be acquired. tACQ is never less than 390ns (AS1530) or 520ns (AS1531), and is calculated by:
tACQ = 9(RS + RIN)18pF (EQ 1) Where:: (EQ 1)
RIN = 800 RS = the source impedance of the input signal.
Note: Source impedances below 2k do not significantly affect the AC performance of the devices.
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Control Register
Data Sheet
Control Register
The control register on the AS1530/AS1531 is a 8-bit, write-only register. Data is written to this register using the CSN, DIN and SCLK pins. The control register format is shown in Table 7 and the function of the bits are defined in Table 8. The AS1530/AS1531 operating modes are selected by sending an 8-bit data word to the internal shift register via pin DIN. After pin CSN is pulled low, the first logic 1 on pin DIN is interpreted as a start bit. A start bit is defined as one of the following: The first logic 1 bit clocked into pin DIN (with CSN low) any time the AS1530/AS1531 is idle, e.g., after VDD1 and VDD2 are applied. ! The first logic 1 bit clocked into pin DIN after bit 6 of a conversion in progress is clocked out of pin DOUT. Figure 22 on page 17 shows the serial-interface timing necessary to perform a conversion every 16 SCLK cycles. If CSN is tied low and SCLK is continuous, guarantee a start bit by first clocking in sixteen 0s. The fastest speed at which the devices can operate is 16 clocks per conversion (with CSN held low between conversions).
!
Table 7. Control Byte Format Bit 7 START (MSB) Bit 6 SEL2 Bit 5 SEL1 Bit 4 SEL0 Bit 3 RANGE Bit 2 MODE Bit 1 PD1 Bit 0 PD0 (LSB)
Table 8. Bit Descriptions Bit 7 Name START Description The first logic 1 bit after CSN goes low signifies the start of a control byte. These three bits select which of the eight channels and pin COM are used for the conversion (see Table 10 and Table 11). This bit selects the analog input range of the AS1530/AS1531. 0 = The analog input range extends from -VREF/2 to +VREF/2. 1= The analog input range extends from 0V to VREF. This bit in conjunction with bit RANGE changes the analog input configuration. 0 = The voltage difference between two selectable channels is converted. This setting selects two's complement coding (see Table 10 on page 16 and Table 11 on page 16). 1 = One of the eight input channels is referenced to COM. This setting also selects binary coding. Selects the AS1530/AS1531 operating mode: PD1 PD0 Mode 0 0 Full power-down mode. 0 1 Reduced-power mode. 1 0 Reduced-power mode. 1 1 Normal operation.
6:4 3
SEL2:SEL0 RANGE
2
MODE
1:0
PD1:PD0
Analog Input Configuration
Table 9. Analog Input Configuration Analog Input Configuration Mode Range Coding Comments AIN+ from 0 to VREF. COM should be tied to GND.
8-Channel Single-Ended 8-Channel Pseudo Differential referenced to COM 8-Channel Pseudo Differential referenced to COM 4-Channel Pseudo Differential 4-Channel Pseudo Differential 4-Channel Fully Differential
1 1 1 0 0 0
1 1 0 1 0 0
Binary Binary Binary Two's Complement Two's Complement Two's Complement
AIN+ from COM to COM + VREF AIN+ from -VREF/2+COM to + VREF/2+COM AIN+ - AIN- from 0 to VREF AIN+ - AIN- from -VREF/2 to +VREF/2 AIN+ - AIN- from -VREF/2 to +VREF/2, fully differential input signal.
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Channel Selection
Data Sheet
Channel Selection
Depending on the setting of bit MODE (page 15), the internal inputs of the ADC (AIN+ and AIN-) are connected differently to the input channels (CH0:CH7 and COM).
Single-Ended Input
Table 10. Input Channel Selection for MODE = 1 SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
AIN+ AIN+ AIN+ AIN+ AIN+ AIN+ AIN+ AIN+
AINAINAINAINAINAINAINAIN-
Note: In single-ended mode pin COM should be connected to GND pin.
Differential Input
Table 11. Input Channel Selection for MODE = 0 SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
AIN+
AINAIN+ AINAIN+ AINAIN+ AIN-
AIN-
AIN+ AINAIN+ AINAIN+ AINAIN+
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Starting a Conversion
Data Sheet
Starting a Conversion
A conversion is started by clocking a control byte into pin DIN. With CSN low, each rising edge on SCLK clocks a bit from DIN into the internal shift register, starting with the MSB. A conversion will only start when a logic 1 is written to the START bit of the 8-bit control register.
Figure 21. Single Conversion Timing Waveforms
CSN tACQ SCLK 1 4 8 9 12 16 20 24
DIN
Start SEL2 SEL1 SEL0
RANGE MODE
PD1
PD0
High-Z SSTRB RB1 High-Z DOUT Idle Acquire
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
High-Z
RB2
RB3 High-Z
Single Conversion
Idle
Figure 22. Continuous 16-Clock Conversion Timing Waveforms
CSN
DIN
S Control Byte 0 1 8 12
S Control Byte 1 16 1 8 12
S Control Byte 2 16 1 8 12
S 16
...
SCLK
High-Z DOUT High-Z SSTRB B11 B6 B0 Conversion Result 0 B11 B6 B0 Conversion Result 1 B11 B6 Conversion Result 2
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Transfer Functions
Data Sheet
Figure 23. Detailed Serial Interface Timing Waveforms
CSN tCSS tCL tCH tCP tCSW
tCSO SCLK tDS
tDH DIN tDOE tSTH tSTV tSTD tDOH tDOV DOUT tDOD
tSTE SSTRB
The external serial clock shifts data in and out of the devices and drives the analog-to-digital conversion steps. Two clock periods after the last bit of the control byte is written the output pin SSTRB pulses high for one clock period. The serial data is shifted out at DOUT on each of the next 12 SCLK rising edges (see Figure 21 on page 17). Pins SSTRB and DOUT go into a high-impedance state when CSN goes high. The conversion must complete in 120s or less, or consequently, droop on the sample-and-hold capacitors may degrade conversion results. Figure 23 shows detailed serial-interface timing waveforms.
Transfer Functions
Output coding and transfer function depend on the control register bits MODE (page 15) and RANGE (page 15).
Figure 24. Straight Binary Transfer Function for RANGE = 1 and MODE = 1
11...111 11...1110 11....101 Full Scale = VREF Zero Scale = 0 1LSB = VREF/4096 Full Scale (FS) Transition
Figure 25. Straight Binary Transfer Function for RANGE = 0 and MODE = 1
11...111 11...1110 11....101 Full Scale = +VREF/2 Zero Scale = -VREF/2 1LSB = VREF/4096 Full Scale (FS) Transition
Output Code
00...011 00...010 00...001 00...000 0 1 2 3 FS - 3/2LSB Input Voltage AIN+ - AIN- (LSB)
00...011 00...010 00...001 00...000 ZS ZS+1LSB FS - 3/2LSB Input Voltage AIN+ - AIN- (LSB)
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Output Code
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Power Modes
Data Sheet
Figure 26. Two's Complement Transfer Function for RANGE = 1 and MODE = 0
011....111 011...110 Full Scale = VREF -Full Scale = 0 Zero Scale = VREF/2 1LSB = VREF/4096
Figure 27. Two's Complement Transfer Function for RANGE = 0 and MODE = 0
011....111 011...110 Full Scale = +VREF/2 -Full Scale = -VREF/2 Zero Scale = 0 1LSB = VREF/4096
Output Code
000...001 000...000 111...111 111...110 111...101
Output Code -FS ZS +FS - 1LSB
000...010
000...010 000...001 000...000 111...111 111...110 111...101
100...001 100...000
100...001 100...000 -FS ZS +FS - 1LSB
Input Voltage AIN+ - AIN- (LSB)
Input Voltage AIN+ - AIN- (LSB)
Power Modes
Power consumption can be reduced by placing the AS1530/AS1531 in reduced power mode or in full power-down mode between conversions. The power mode is selected using bits PD1 and PD0 of the 8-bit control byte. Table 12 lists the three operating modes with the corresponding supply current and active device circuits. For data rates achievable in full power-down mode (see Full Power-Down Mode on page 20).
Table 12. Software Controlled Power Modes PD1/PD0 (page 23) Total Supply Current Mode During Conversion AS1530 AS1531 After Conversion AS1530 AS1531 Device Circuits Input Comparator
*
Reference
00 01 10 11
*
Full Power-Down Mode Reduced-Power Mode Normal Operation
2.8mA 2.8mA 2.8mA
2.2mA 2.2mA 2.2mA
0.5A 0.4mA 2.0mA
0.5A 0.4mA 1.8mA
Off Reduced Power Full Power
Off On On
Circuit operation between conversions; during conversion all circuits are fully powered up.
The selected power-down mode (as shown in Table 12) is initiated after an analog-to-digital conversion is completed. In all power modes the serial interface remains active, waiting for a new control byte to start conversion (see Figure 30 on page 21). Once the conversion is completed, the AS1530/AS1531 goes into the selected power mode until a new control byte is shifted in. In reduced power mode the AS1530/AS1531 will be able to start conversion immediately when running at decreased clock rates. In full power down mode wait until the internal reference has stabilized (dependant on the values of the capacitance of REF and REFADJ). During initialization the AS1530/AS1531 immediately go into normal operation mode and are ready to convert after 4s when using an external reference. When using the internal reference, wait until the internal reference has stabilized (dependant on the values of the capacitance of REF and REFADJ).
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Power Modes
Data Sheet
Reduced Power Mode
Reduced power mode is activated using bits PD1 and PD0 (see Table 12). When reduced power mode is asserted, the AS1530/AS1531 completes any conversion in progress and enters reduced power mode. The next start of conversion puts the AS1530/AS1531 into normal operation mode. The 8-bit control byte shifted into the control register determines the next power mode. For example, if the 8-bit control byte contains PD1 = 0 and PD0 = 1, reduced power down mode starts immediately after the conversion (see Figure 28). The reduced-power mode achieves the lowest power consumption at speeds close to the maximum sample rate. Figure 29 shows the AS1531 power consumption in reduced-power mode and normal operating mode (see Table 12 on page 19) with the internal reference and maximum clock speed.
Figure 28. Reduced-Power Mode Timing Waveforms (AS1531)
DIN
1 ReducedPower
10
1 ReducedPower 2.50V (Always On)
10
1 ReducedPower
01
REF 2.2mA VDD1+VDD2 +VDD3 Normal Mode Conversion
2.2mA 0.4mA Reduced Power Down Normal Mode Conversion 0.4mA Reduced Power Down
2.2mA Normal Mode Conversion 0.4mA Reduced Power Down
Note: The clock speed in reduced-power mode should be limited to 4.8MHz. Full power-down mode may provide increased power savings in applications where the devices are inactive for long periods of time, where intermittent bursts of high-speed conversions are required. Figure 29. Normal Operation and Reduced Power Down using Internal Reference (AS1531)
3000 2500
Normal Operation
Supply Current (A) .
2000 1500 1000
Reduced Power Mode
500 0 0.001
0.1
10
1000
Sampling Rate (ksps)
Full Power-Down Mode
Full power-down is activated using bits PD1 and PD0 (see Table 12). Full power-down mode offers the lowest power consumption at up to 1000 conversions per-channel per-second. When full power-down is asserted, the AS1530/ AS1531 completes any conversion in progress and powers down into specified low-quiescent current state. The start of the next conversion puts the AS1530/AS1531 into normal operation mode. The 8-bit control byte shifted into the control register determines the next power mode. For example, if the 8-bit control byte contains PD1 = 0 and PD0 = 0, full power-down mode starts immediately after the conversion (see Figure 30 on page 21)
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Reference
Data Sheet
A 0.01F bypass capacitor plus the internal 17k reference resistor at REFADJ form an R/C filter with a 200s time constant. To achieve full 12-bit accuracy, 10 time constants (2ms) are required after power-up if the bypass capacitor is fully discharged between conversions. Waiting this 2ms in reduced-power mode instead of normal operation mode can further reduce power consumption. This is achieved by using the sequence shown in Figure 30 on page 21. Figure 31 on page 21 shows the AS1531 power consumption for conversions using full power-down mode (PD1 = PD0 = 0 (see Table 12), an external reference, and the maximum clock speed. One dummy conversion to power-up the device is required, but no wait-time is necessary to start the second conversion, thereby achieving lower power consumption up to the full sampling rate.
Figure 30. Full Power-Down Timing Waveforms (AS1531)
1 DIN
00 Full PowerDown
1
10 ReducedPower
1
00 Full PowerDown
1
REFADJ
1.22V
1.22V
= R/C = 17k x 0.01F
REF 2.5V 2.5V
IVDD1+IVDD2 +IVDD3
2.2mA Normal Mode Conversion 0mA Full PowerDown
2.2mA Normal Mode Dummy Conversion 0.4mA Reduced Power Down
2.2mA Normal Mode Conversion 0mA Full PowerDown
Figure 31. Average Supply Current vs. Sampling Rate (AS1531, FULLPD, and External Reference)
100000
Supply Current (A) .
100
1 Channel
0.1 0.001
0.01
0.1
1
10
100
Sampling Rate (ksps)
Reference
The AS1530/AS1531 can operate with the internal or an external reference.
Internal Reference
The internal reference is selected by placing a capacitor between REFADJ and GND. The internally trimmed 1.22V bandgap voltage available at REFADJ is buffered with a gain of 2.045V/V to pin REF, where 2.5V are available. A decoupling capacitor is needed at pin REF.
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Reference
Data Sheet
Additionally the bandgap voltage can be adjusted about 100mV by forcing a voltage to the REFADJ pin. The REFADJ input impedance is typically 17k. Figure 32 shows a possible arrangement.
Figure 32. Reference Adjust Circuit
+3.3V 24k 100k 510k CLOAD 0.01F DGND GND 12 REFADJ
AS1530/ AS1531
External Reference
An external reference can be connected directly at pin REF. To use the external reference, the internal buffer must be disabled by connecting pin REFADJ to pin VDD. The input resistance is typically 15k. During conversion, an external reference at pin REF must deliver up to 350A DC load current and have 10 or less output impedance. If the reference has a higher output impedance or is noisy, bypass it with a 4.7F capacitor placed as close to pin REF as possible.
Note: Using the REFADJ input makes buffering the external reference unnecessary.
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Initialization
Data Sheet
9 Application Information
Initialization
When power is first applied to the AS1530/AS1531 internal power-on reset circuitry sets the devices for normal operation. At this point, the devices can perform data conversions with CSN held low.
Note: The device requires 10s after the power supplies stabilize; no conversions should be initiated during this time.
The digital output at pin DOUT will be all 0s until an analog-to-digital conversion is initiated.
Serial Interface
The AS1530/AS1531 fully support SPI, QSPI, and Microwire interfaces. For SPI, select the correct clock polarity and sampling edge in the SPI control registers (set CPOL = 0 and CPHA = 0).
Note: Microwire, SPI, and QSPI all transmit a byte and receive a byte at the same time.
Using the circuit shown in Figure 33 on page 24, the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the AS1530/AS1531, and two more 8-bit transfers to clock out the 12-bit conversion result).
Serial Interface Configuration
The following steps describe how to configure the serial interface: 1. Confirm that the CPU serial interface is in master mode (so the CPU generates the serial clock). 2. Choose a clock frequency from 500kHz to 6.4MHz (AS1530) or 4.8MHz (AS1531). 3. Set up the control byte and call it TB1. TB1 should be in the format 1XXXXXXX binary, where the Xs indicate the selected channel, conversion mode, and power mode. 4. Use a general-purpose I/O line on the CPU to pull CSN low. 5. Transmit TB1 and simultaneously receive a byte (RB1). Ignore this byte. 6. Transmit a byte of all zeros ($00h) and simultaneously receive byte RB2. 7. Transmit a byte of all zeros ($00h) and simultaneously receive byte RB3. 8. Pull CSN high. Bytes RB2 and RB3 (see Figure 21) contain the results of the conversion, padded with three leading zeros and one trailing zero. The total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive track/hold droop, make sure the total conversion time does not exceed 120s.
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Serial Interface
Data Sheet
Figure 33. Operational Diagram
+3 to +5V 1 CH0 20 VDD1 19 VDD2 10 VDD3 13 GND 0.1F VDD 10F
+2.5V Analog Inputs
. . .
8 CH7 9 COM 11 REF 12 REFADJ
AS1530/ AS1531
17 CSN 18 SCLK 16 DIN 14 DOUT 15 SSTRB I/O SCK (SK) MOSI (SO) MISO (SI) VSS
CPU
4.7F
0.1F
QSPI Interface
The AS1530/AS1531 can interface with QSPI using the circuit in Figure 34 (fSCLK = 4.0MHz, CPOL = 0, CPHA = 0). This QSPI circuit can be programmed to do a conversion on each of the eight channels. The result is stored in memory without affecting CPU performance, since QSPI incorporates a micro-sequencer.
Figure 34. QSPI Interface Connections
1 CH0 20 VDD1 19 VDD2 10 VDD3 13 GND 0.1F +3 or +5V + 10F
+2.5V Analog Inputs
. . .
8 CH7 9 COM 11 REF 12 REFADJ
AS1530/ AS1531
17 CSN 18 SCLK 16 DIN 14 DOUT 15 SSTRB
CPU
PCSO SCK MOSI MISO
Power Supplies
+3 or +5V
GND
4.7F
0.1F
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Quick Evaluation Circuit
Data Sheet
Quick Evaluation Circuit
In order to quickly evaluate the analog performance of the AS1530/AS1531, use the circuit shown in Figure 35.
Figure 35. Evaluation Circuit Diagram
20 VDD1 19 VDD2 10 VDD3 8 CH7 0.1F 13 GND 0.1F 10F +3 or +5V
+2.5V Analog Input
AS1530/ AS1531
9 COM 11 REF 12 REFADJ
17 CSN 18 SCLK 16 DIN 14 DOUT 15 SSTRB To VDD2 TBA External Clock
4.7F
0.1F
Connecting DIN to VDD2 shifts in control bytes of $FFh, which trigger single-ended conversions (bit RANGE (page 15) = 1) on CH7 without powering down between conversions. The SSTRB output pulses high for one clock period before the MSB of the 12-bit conversion result is shifted out of DOUT. Varying the analog input to CH7 will alter the sequence of bits from DOUT. A total of 16 clock cycles is required per conversion.
Note: All SSTRB and DOUT output transitions occur 25ns (typ) after the rising edge of SCLK.
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Layout Considerations
Data Sheet
Layout Considerations
The AS1530/AS1531 require proper layout and design procedures for optimum performance.
! ! ! !
Use printed circuit boards; wirewrap boards should not be used. Analog and digital traces should be separate and should not run parallel to each other (especially clock traces). Digital traces should not run beneath the AS1530/AS1531. Use a single-point analog ground at GND, separate from the digital ground (see Figure 36). Connect all other analog grounds and DGND to this star ground point for further noise reduction. No other digital system ground should be connected to this single-point analog ground. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the VDD power supply may affect the AS1530/AS1531 high-speed comparator. Bypass this supply to the single-point analog ground with 0.1F and 4.7F bypass capacitors. Bypass capacitors should be as close to the device as possible for optimum power supply noise-rejection. If the power supply is very noisy, a 10 resistor can be connected as a low-pass filter to attenuate supply noise (see Figure 36).
!
Figure 36. Recommended GND Design
GND
DGND
Digital Circuitry
VDD2 +
VDD 19 VDD2 9 COM 13
Power Supplies
GND + VDD1 10 (Optional)
GND 20 VDD1 10 VDD3
AS1530/ AS1531
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Data Sheet
10 Package Drawings and Markings
Figure 37. 20-pin TSSOP Package
Notes:
1. All dimensions are in millimeters; angles in degrees. 2. Dimensioning and tolerancing per ASME Y14.5M - 1994. 3. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, and gate burrs shall not exceed 0.15mm per side. 4. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. 6. Terminal numbers are for reference only. 7. Datums A and B to be determined at datum plane H. 8. Dimensions D and E1 are to be determined at datum plane H. 9. This dimension applies only to variations with an even number of leads per side. 10. Cross section A-A to be determined at 0.10 to 0.25mm from the leadtip.
Symbol A A1 A2 L R R1 b b1 c c1 1 L1 aaa bbb ccc ddd e 2 3
D E1 E e N
Typ 0.90 0.60 0.22 1.0REF 0.10 0.10 0.05 0.20 0.65BSC 12REF 12REF Variations 6.40 6.50 4.30 4.40 6.4BSC 0.65BSC 20
Min 0.05 0.85 0.50 0.09 0.09 0.19 0.19 0.09 0.09 0
Max 1.10 0.15 0.95 0.75 0.30 0.25 0.20 0.16 8
Notes 1,2 1,2 1,2 1,2 1,2 1,2 1,2,5 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2
6.60 4.50
1,2,3,8 1,2,4,8 1,2 1,2 1,2,6
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Data Sheet
11 Ordering Information
The devices are available as the standard products shown in Table 13.
Table 13. Ordering Information Model Description Delivery Form Package
AS1530-T AS1530 AS1531-T AS1531
12-bit ADC, 8-channel, 400ksps 12-bit ADC, 8-channel, 400ksps 12-bit ADC, 8-channel, 300ksps 12-bit ADC, 8-channel, 300ksps
Tape and Reel Tubes Tape and Reel Tubes
20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP
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Data Sheet
Copyrights
Copyright (c) 1997-2006, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria
Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 e-mail: info@austriamicrosystems.com For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com
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